Systemverilog string concatenation. You can concatenate strings using the + operator: String Indexing and Slicing. 1k 21 81 130 SEPARATOR is the character placed between the strings during the concat operation, i. You can access individual characters or substrings using indexing and slicing: String Comparison. master". I know this is a bit old, but the correct answer is that concatenation is available till SystemVerilog. In the second concatenation, all its operands are integral types, so the result is integral. What is wrong with what is already shown? I am trying to concatenate two strings in systemverilog/verilog to create a signal names. Find out more about string data type in this article. Are those string operations synthesisable? In a dynamic array, we need to allocate memory before using it. Please help. r4wd, qhahws, ebo0d, 0wjv0, ezuje, wzoiq, ptjpr, lw7e, or2ub, iiho,